Due to structural simplicity, DRAMs (dynamic random access memories) can provide more memory cells per unit chip area than other types of memories such as static random access memories. A DRAM is constituted by a plurality of DRAM cells, each of which includes a capacitor for storing information and a transistor coupled to the capacitor for regulating when the capacitor is to be charged or discharged. During a read operation, a word line is asserted, turning on the transistor. The enabled transistor allows the voltage across the capacitor to be read by a sense amplifier through a bit line. During a write operation, the data to be written is provided on the bit line while the word line is asserted.
To satisfy the demand for greater memory storage, DRAM memory cells need size reduction. DRAM memory cell size can be reduced in several ways. One way is to reduce the minimum feature size of a DRAM memory cell through the advances in process technology. Another way to reduce the size of a DRAM memory cell is by designing a memory cell having a smaller feature size. For example, many DRAM chips on the market today have a memory cell size of 4F2, where F stands for the photolithographic minimum feature width or critical dimension (CD).
Referring to FIGS. 1 to 9, a conventional method for preparing a recess array device structure for the 4F2 memory cell is illustrated. Referring to FIG. 1, a base material 1 is provided. It should be noted that FIG. 1 is a top view of the base material 1. The base material 1 comprises a semiconductor substrate 12, a first material 14 and an interlaying material 13. The semiconductor substrate 12 has a plurality of first recesses 121 and a plurality of interlaying recesses 122. That is, the first recesses 121 and the interlaying recesses 122 are formed on the semiconductor substrate 12 in a preceding step. The interlaying recesses 122 are parallel to the first recesses 121, and each of the interlaying recesses 122 is disposed between two first recesses 121.
The first material 14 is disposed in the first recesses 121, and the interlaying material 13 is disposed in the interlaying recesses 122. That is, the first material 14 and the interlaying material 13 are formed in a preceding step. The semiconductor substrate 12 is a silicon substrate, and the first material 14 is oxide. The interlaying material 13 includes a liner layer 132 and a center oxide 131. Usually, the liner layer 132 includes a liner oxide layer and a liner nitride layer.
Referring to FIGS. 2 and 3, a first covering layer 21 is formed on the base material 1 to cover the semiconductor substrate 12, the first recesses 121 and the interlaying recesses 122. A second covering layer 22 is formed on the first covering layer 21. A third covering layer 23 is formed on the second covering layer 22. A photoresist layer 24 is formed on the third covering layer 23. It should be noted that FIG. 3 is a cross-sectional view of FIG. 2 taken along line 3-3. The first covering layer 21 is polysilicon, the second covering layer 22 is carbon, and the third covering layer 23 is silicon oxynitride (SiON). Next, the photoresist layer 24 is patterned to form a plurality of photoresist layer openings 241 to expose part of the third covering layer 23.
Referring to FIG. 4, the third covering layer 23, the second covering layer 22, the first covering layer 21 and the base material 1 are etched according to the photoresist layer openings 241 so as to form a plurality of second recesses 31. The second recesses 31 intersect the first recesses 121. Usually, the second recesses 31 are perpendicular to the first recesses 121 from a top view. Next, the photoresist layer 24, the third covering layer 23 and the second covering layer 22 are all removed, and the first covering layer 21 remains.
Referring to FIGS. 5 and 6, a second material 32 is formed in the second recesses 31. It should be noted that FIG. 6 is a cross-sectional view of FIG. 5 taken along line 6-6. The second material 32 includes a liner layer 322 and a center oxide 321. Usually, the liner layer 322 includes a liner oxide layer and a liner nitride layer.
Referring to FIGS. 7 and 8, the first covering layer 21 is removed so that the second material 32 protrude from the base material 1. Next, a plurality of spacers 33 are formed on the side walls of the protruded second material 32. The spacers 33 is oxide or nitride.
Referring to FIG. 9, the base material 1 is etched according to the gaps between the spacers 33 so as to form a plurality of third recesses 34. The third recesses 34 intersect the first recesses 121 and are parallel to the second recesses 31.
Next, the protruded second material 32 and the spacers 33 are removed. Finally, a third material (not shown) is formed in the third recesses 34. The third material 34 is oxide.
The drawback of the above-mentioned conventional method is as follows. Since the base material 1 comprises a semiconductor substrate 12 (which is silicon) and a first material 14 (which is oxide), the etching process of FIG. 9 is a non-selective etching process. It is difficult to get enough selectivity when the feature size becomes 20 nm or beyond. Further, The spacers 33 (FIG. 8) is oxide or nitride. The spacer 33 must be very tall to resist the etching gas.